As the miniaturization of integrated circuits progresses, the measurement of timing parameters is a big challenge. Two main challenges are to measure the timing width of a very small pulse with high accuracy in any general digital circuit and to achieve a high resolution, e.g. around 1 ps.
The small pulse width measurement is an important step for many applications, for example: 1) exact timing characterization of silicon standard cells library, 2) measuring the critical path delay time on the chip in silicon, 3) measuring actual hold time on the chip in silicon, 4) measuring rising and fall slew rate on chip in silicon, and 5) SRAM access time detection, etc.
However, very accurate timing characteristics for cell delay measurement are very difficult to achieve with high resolution due to scaling values of cell timing characteristics with scaling technology and limitations on automatic tester equipment (ATE) such as coarse resolution etc. Conventional methods suffer from very low resolution, have difficulty getting the on-chip digital data, capturing large volumes of data in short time, and measuring rise and fall slew rate using normal ATE. Also, they require using a long delay chains or averaging out mechanism to overcome problems of coarse resolution, etc.
Accordingly, new methods for high-resolution timing measurement with better accuracy are desired.